Northwestern University

Fri 11:00 PM

Prof. Natalie Enright Jerger: Application-Aware Network-on-Chip Architectures

When: Friday, January 11, 2013
11:00 PM - 12:00 PM  

Where: Technological Institute, L324, 2145 Sheridan Road, Evanston, IL 60208 map it

Audience: Faculty/Staff - Student - Public

Contact: Lana Kiperman   847.467.0028

Group: Electrical Engineering & Computer Science

Category: Lectures & Meetings

More Info


The EECS Department welcomes Assistant Professor Natalie Enright Jerger of The Edward S. Rogers Sr. Dept. of Electrical and Computer Engineering at the University of Toronto.

Prof. Jerger will present a lecture on Friday January 11 entitled "Application-Aware Network-on-Chip Architectures"  

Abstract:  As transistors continue to scale according to Moore’s Law, efficient and scalable communication mechanisms will be required to realize the performance potential of many-core architectures.  The increased demand for on-chip communication and the poor scaling of long global wires have made packet-switched networks-on-chip (NoC) a compelling choice for the communication backbone in these next-generation systems.  Current NoC architectures are largely agnostic to the communication demands of the applications and the underlying architecture.  In this talk, I will discuss research which explores increasing the functionality within the NoC to better match application demands.  First, I will present a novel flow control technique that improves performance and buffer utilization in the face of short coherence control packets. Short control packets arise in NoCs due to abundant wiring resources. Second, I will present NoC support for routing collective communication.   

Please click the "More Info" link above to read the full abstract and Prof. Jerger's bio.

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